1. Field of the Invention
The present invention relates to an insulated gate field effect transistor (IGFET) operated with a low gate voltage and a high source and drain voltage, for use in a circuit such as a level shifter in a scan electrode or signal electrode drive integrated circuit for a liquid crystal display (LCD) device. More particularly, the invention relates to improvements of the transistor structure.
2. Description of the Prior Art
A driver section for an n-th signal electrode (n-th output) in a signal electrode drive IC (Y driver) of the 4-level type that is used in an LCD device is shown in FIG. 7. The signal electrode is made up of a latch circuit Ln, operated by a low level logic powder source of 3 V or 5 V, for latching display data for one horizontal period, a level shifter LSn for shifting a low level logic amplitude (between 0 V and 3 V or 5 V) of the latched display data to a high level logic amplitude (between 0 V and 55 V), a decoder Dn for decoding display data signals of a high level logic amplitude and liquid crystal conversion-to-AC signals FR of a high level logic amplitude (between 0 V and 55 V). The signal electrode also includes a voltage selector Sn for selecting one of voltage VDDH (55 V), V3 (45 V), V4 (10 V), and V6 (0 V) in accordance with a select signal of a high level logic amplitude from the decoder and for applying the selected voltage to the n-th output Qn.
A circuit including the latch circuit Ln operates as a low breakdown voltage section Lv for a power source of 3 V or 5 V. A circuit including the level shifter Lsn, the decoder, and the voltage selector Sn operates as a high breakdown voltage section Hv for a power source of 55 V, for example. A plurality of CMOS transistors (complementary insulated gate field effect transistors) are fabricated into these sections.
A CMOS device which includes circuit elements for both low and high breakdown voltage sections Lv and Hv and a method of manufacturing the same are disclosed in U.S. patent application Ser. No. 08/053273 (Japanese Patent Application No. 4-111330). The CMOS gate structure including a low and a high voltage breakdown section will briefly be described in accordance with FIG. 8. The semiconductor device 1 shown in FIG. 8 is a driver IC for an LCD flat panel display device. The driver IC includes a low voltage drive circuit section 1a and a high voltage drive circuit section 1b, which are both formed in the surface region of a monocrystal silicon substrate 100 (semiconductor substrate).
The low voltage drive circuit section 1a is driven at a drive voltage of 5 V or lower. Circuit section la includes a low voltage N-channel IGFET 101 and a low voltage P-channel IGFET 102, both forming a CMOS structure. The low voltage P-channel IGFET 102, formed in the surface region of an N-well of the monocrystal silicon substrate 100, includes a gate oxide film 12 approximately 250 .ANG. thick, a gate electrode 13b made of N-type impurity doped polysilicon, and a P+-type source and drain region 15a. The gate oxide films 12 are approximately 250 .ANG. in thickness. The low voltage N-channel IGFET 101 and the low voltage P-channel IGFET 102 are designed to be operable at high speeds.
The high voltage drive circuit section 1b is driven at a voltage of several tens of volts or higher. Circuit section 1b includes a high voltage N-channel IGFET 103 and a high voltage P-channel IGFET 104, both forming a CMOS structure. The low voltage N-channel IGFET 101, formed in the surface region of a P-well of a monocrystal silicon substrate 100, includes a gate oxide film 12 of approximately 250 .ANG. thick, a gate electrode 13a made of N-type impurity doped polysilicon, and an N+-type source and drain region 14a. The high voltage N-channel IGFET 103, formed in the surface region of a P-well of the monocrystal silicon substrate 100, includes a gate oxide film 10 approximately 1300 .ANG. or greater in thickness, a gate electrode 11a made of N-type impurity doped polysilicon, and an N+-type source and drain region 14b formed in the surface region of an N-type offset diffusion layer 6 of low impurity concentration. The high voltage P-channel IGFET 104, formed in the surface region of an N-well of the monocrystal silicon substrate 100, incudes a gate oxide film 10 approximately 1300 .ANG. or greater in thickness, a gate electrode 11b made of P-type impurity doped polysilicon, and a P+-type source and drain region 15b formed in the surface region of a P-type offset diffusion layer 5 of low impurity concentration. The gate oxide films 10 are approximately 1300 .ANG. or greater in thickness. The high voltage N-channel IGFET 103 and the high voltage P-channel IGFET 104 are designed to have a high breakdown voltage.
In FIG. 8, reference numeral 7 designates an N+ guard ring; 8, a P+ guard ring; and 9, a field oxide film. In the structure of FIG. 8, those portions other than the gate oxide films, which are also designated by reference numeral 12, are formed in the same manner as gate oxide films 12.
In the CMOS structure described above, the CMOS elements in the low voltage drive circuit have thin gate insulating films. The CMOS elements in the high voltage drive circuit include thick gate insulating films and drain in the offset diffusion region of low impurity concentration.
In semiconductor integrated circuits using both low and high voltage power sources, it is sometimes difficult to classify the circuit elements into those exclusively in the low breakdown voltage section Lv and those exclusively in the high breakdown voltage section Hv. For example, in the signal electrode drive IC of the 4-level type shown in FIG. 7, the level shifter LSn located in the boundary region between the low and high breakdown voltage section Lv and Hv may be electrically constructed as shown in FIG. 9. The level shifter receives an output signal of a low level logic amplitude from the latch circuit Ln driven by a low voltage power source (3 V or 5 V) and a high voltage power source VDDH (55 V), and outputs a logic signal of a high level logic amplitude.
In the circuit of FIG. 9, the gate insulating films of P-channel MOS transistors P1 and P2 are thick, e.g., approximately 1500 .ANG.. The same is true for N-channel MOS transistors N1 and N2. Application of low gate voltage of about 5 V to a gate insulating film of approximately 1500 .ANG. thick does not provide a sufficient drive ability (current capacity) when the MOS transistors N1 and N2 are in an on state. For this reason, the CMOS elements are unsuitable for a high speed operation.
In the recent trend of using a 3 V power source for driving a low breakdown voltage section, the drive ability of the latch circuit Ln output is further reduced. In an extreme case, the latch circuit becomes inoperable.